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» Instruction Pre-Processing in Trace Processors
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SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
15 years 2 months ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...
HPCA
2000
IEEE
15 years 2 months ago
Decoupled Value Prediction on Trace Processors
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
Sang Jeong Lee, Yuan Wang, Pen-Chung Yew
ICPP
1999
IEEE
15 years 1 months ago
Trace-Level Reuse
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...
Antonio González, Jordi Tubella, Carlos Mol...
ISCA
2000
IEEE
92views Hardware» more  ISCA 2000»
15 years 1 months ago
Trace preconstruction
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
Quinn Jacobson, James E. Smith
IEEEPACT
1999
IEEE
15 years 1 months ago
The Effect of Program Optimization on Trace Cache Efficiency
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
Derek L. Howard, Mikko H. Lipasti