Sciweavers

59 search results - page 6 / 12
» Instruction Pre-Processing in Trace Processors
Sort
View
ICS
1999
Tsinghua U.
15 years 1 months ago
Software trace cache
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...
IPCCC
1999
IEEE
15 years 1 months ago
Accurately modeling speculative instruction fetching in trace-driven simulation
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
R. Bhargava, L. K. John, F. Matus
ICPP
2002
IEEE
15 years 2 months ago
Out-of-Order Instruction Fetch Using Multiple Sequencers
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
Paramjit S. Oberoi, Gurindar S. Sohi
VEE
2009
ACM
246views Virtualization» more  VEE 2009»
15 years 4 months ago
Tracing for web 3.0: trace compilation for the next generation web applications
Today’s web applications are pushing the limits of modern web browsers. The emergence of the browser as the platform of choice for rich client-side applications has shifted the ...
Mason Chang, Edwin W. Smith, Rick Reitmaier, Micha...
HICSS
1994
IEEE
118views Biometrics» more  HICSS 1994»
15 years 1 months ago
A Distributed Architecture for an Instructable Problem Solver
Our research goal is to design systems that enable humans to teach tedious, repetitive, simple tasks to a computer. We propose here a learner/problem solver architecture for such ...
Jacky Baltes, Bruce A. MacDonald