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» Instruction Pre-Processing in Trace Processors
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POPL
2008
ACM
15 years 10 months ago
Formal verification of translation validators: a case study on instruction scheduling optimizations
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
Jean-Baptiste Tristan, Xavier Leroy
ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
15 years 1 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...
ICCD
2002
IEEE
130views Hardware» more  ICCD 2002»
15 years 6 months ago
Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors
This paper presents a detailed branch characterization of an Oracle based commercial on-line transaction processing workload, Oracle Database Benchmark (ODB), running on an IA32 p...
Murali Annavaram, Trung A. Diep, John Paul Shen
JUCS
2000
120views more  JUCS 2000»
14 years 9 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
PLDI
2005
ACM
15 years 3 months ago
Code placement for improving dynamic branch prediction accuracy
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...
Daniel A. Jiménez