59 search results - page 9 / 12 » Instruction Pre-Processing in Trace Processors |
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
60
Voted
HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
72
Voted
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
SIGSOFT
2006
ACM
15 years 10 months ago
2006
ACM
Fixing runtime bugs in long running programs using trace based analyses such as dynamic slicing was believed to be prohibitively expensive. In this paper, we present a novel execu...