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» Instruction Scheduling and Executable Editing
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MICRO
1996
IEEE
81views Hardware» more  MICRO 1996»
13 years 10 months ago
Instruction Scheduling and Executable Editing
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and a...
Eric Schnarr, James R. Larus
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
13 years 10 months ago
Speculation Techniques for Improving Load Related Instruction Scheduling
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan...
PLDI
1995
ACM
13 years 9 months ago
EEL: Machine-Independent Executable Editing
EEL (Executable Editing Library) is a library for building tools to analyze and modify an executable (compiled) program. The systems and languages communities have built many tool...
James R. Larus, Eric Schnarr
IPPS
1999
IEEE
13 years 10 months ago
Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions
VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set archit...
Alberto Ferreira de Souza, Peter Rounce
ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
13 years 11 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti