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» Instruction Scheduling and Executable Editing
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CASES
2003
ACM
15 years 2 months ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 1 months ago
Unconstrained Speculative Execution with Predicated State Buffering
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masa...
IPPS
2000
IEEE
15 years 2 months ago
On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
Alberto Ferreira de Souza, Peter Rounce
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 1 months ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain
MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
15 years 1 months ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...