7 search results - page 2 / 2 » Instruction Scheduling for Variation-Originated Variable Lat... |
PPL
2006
14 years 11 months ago
2006
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
115
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MICRO
2010
IEEE
14 years 10 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...