22 search results - page 3 / 5 » Instruction Scheduling with Release Times and Deadlines on I... |
LCTRTS
2001
Springer
13 years 10 months ago
2001
Springer
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
APCSAC
2001
IEEE
13 years 10 months ago
2001
IEEE
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
ACSC
2004
IEEE
13 years 10 months ago
2004
IEEE
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
CONCURRENCY
2006
13 years 6 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
ESA
2007
Springer
14 years 13 days ago
2007
Springer
The aim of power management policies is to reduce the amount of energy consumed by computer systems while maintaining satisfactory level of performance. One common method for savin...