188 search results - page 10 / 38 » Instruction Set Extension Exploration in Multiple-Issue Arch... |
111
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DAC
2008
ACM
16 years 18 days ago
2008
ACM
We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run...
93
Voted
LCTRTS
2007
Springer
15 years 5 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
195
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ASPLOS
2009
ACM
16 years 7 days ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
92
Voted
IPPS
2000
IEEE
15 years 4 months ago
2000
IEEE
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
ASPLOS
2006
ACM
15 years 3 months ago
2006
ACM
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...