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99
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EUROPAR
2000
Springer
15 years 3 months ago
Automatic SIMD Parallelization of Embedded Applications Based on Pattern Recognition
This paper investigates the potential for automatic mapping of typical embedded applications to architectures with multimedia instruction set extensions. For this purpose a (patter...
Rashindra Manniesing, Ireneusz Karkowski, Henk Cor...
101
Voted
ICCAD
2005
IEEE
141views Hardware» more  ICCAD 2005»
15 years 8 months ago
Architecture and compilation for data bandwidth improvement in configurable embedded processors
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
Jason Cong, Guoling Han, Zhiru Zhang
IEEEPACT
2002
IEEE
15 years 4 months ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall
100
Voted
RSP
2003
IEEE
103views Control Systems» more  RSP 2003»
15 years 4 months ago
An Instruction Throughput Model of Superscalar Processors
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
Tarek M. Taha, D. Scott Wills
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...