188 search results - page 16 / 38 » Instruction Set Extension Exploration in Multiple-Issue Arch... |
SBACPAD
2009
IEEE
15 years 6 months ago
2009
IEEE
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
89
Voted
WSC
1997
15 years 1 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
90
Voted
ICLP
1993
Springer
15 years 3 months ago
1993
Springer
nt an abstract instruction set for a constraint solver over finite domains, which can be smoothly integrated in the WAM architecture. It is based on the use of a single primitive...
ASPDAC
2001
ACM
15 years 3 months ago
2001
ACM
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
TPDS
2010
14 years 10 months ago
2010
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...