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110
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JAR
2006
103views more  JAR 2006»
14 years 11 months ago
A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures
We describe an approach to verifying bit-level pipelined machine models using a combination of deductive reasoning and decision procedures. While theorem proving systems such as AC...
Panagiotis Manolios, Sudarshan K. Srinivasan
IPPS
2005
IEEE
15 years 5 months ago
An Empirical Study On the Vectorization of Multimedia Applications for Multimedia Extensions
Multimedia extensions (MME) are architectural extensions to general-purpose processors to boost the performance of multimedia workloads. Today, in-line assembly code, intrinsic fu...
Gang Ren, Peng Wu, David A. Padua
109
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DATE
2007
IEEE
142views Hardware» more  DATE 2007»
15 years 6 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...
137
Voted
CAMP
2005
IEEE
15 years 5 months ago
Speeding-up NCC-Based Template Matching Using Parallel Multimedia Instructions
— This paper describes the mapping of a recently introduced template matching algorithm based on the Normalized Cross Correlation (NCC) on a general purpose processor endowed wit...
Luigi di Stefano, Stefano Mattoccia, Federico Tomb...
ISCA
1989
IEEE
1033views Hardware» more  ISCA 1989»
15 years 3 months ago
Can Dataflow Subsume von Neumann Computing?
: We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?’’ Starting with a simple, “RISC-like” ins...
Rishiyur S. Nikhil