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SIGOPS
2011
255views Hardware» more  SIGOPS 2011»
14 years 6 months ago
Bridging functional heterogeneity in multicore architectures
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
Dheeraj Reddy, David A. Koufaty, Paul Brett, Scott...
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 1 days ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
15 years 1 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
FPL
2010
Springer
267views Hardware» more  FPL 2010»
14 years 9 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
FCCM
2002
IEEE
156views VLSI» more  FCCM 2002»
15 years 4 months ago
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64
The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing re...
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, ...