Sciweavers

188 search results - page 23 / 38
» Instruction Set Extension Exploration in Multiple-Issue Arch...
Sort
View
MASCOTS
2010
15 years 1 months ago
Barra: A Parallel Functional Simulator for GPGPU
Abstract--We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the na...
Sylvain Collange, Marc Daumas, David Defour, David...
ERSA
2007
177views Hardware» more  ERSA 2007»
15 years 1 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
SOSP
2007
ACM
15 years 8 months ago
Secure virtual architecture: a safe execution environment for commodity operating systems
This paper describes an efficient and robust approach to provide a safe execution environment for an entire operating system, such as Linux, and all its applications. The approach...
John Criswell, Andrew Lenharth, Dinakar Dhurjati, ...
CODES
2006
IEEE
15 years 1 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
MICRO
2007
IEEE
159views Hardware» more  MICRO 2007»
15 years 6 months ago
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
Kypros Constantinides, Onur Mutlu, Todd M. Austin,...