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79
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IPPS
2006
IEEE
15 years 3 months ago
An automated development framework for a RISC processor with reconfigurable instruction set extensions
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
Nikolaos Vassiliadis, George Theodoridis, Spiridon...
IPPS
2006
IEEE
15 years 3 months ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
72
Voted
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 3 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
97
Voted
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
15 years 3 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
ICPPW
2006
IEEE
15 years 3 months ago
Multidimensional Dataflow-based Parallelization for Multimedia Instruction Set Extensions
In retargeting loop-based code for multimedia instruction set extensions, a critical issue is that vector data types of mixed precision within a loop body complicate the paralleli...
Lewis B. Baumstark Jr., Linda M. Wills