369 search results - page 11 / 74 » Instruction set mapping for performance optimization |
108
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HIPEAC
2007
Springer
15 years 3 months ago
2007
Springer
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
128
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IEEEPACT
2005
IEEE
15 years 5 months ago
2005
IEEE
Feedback-directed Optimization has become an increasingly important tool in designing and building optimizing compilers as itprovides a means to analyze complexprogram behavior th...
110
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ISCAS
2005
IEEE
15 years 5 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
ASPLOS
2006
ACM
15 years 3 months ago
2006
ACM
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
124
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HPDC
2012
IEEE
13 years 2 months ago
2012
IEEE
This paper presents a scheme to optimize the mapping of HPC applications to a set of hybrid dedicated and cloud resources. First, we characterize application performance on dedica...