369 search results - page 16 / 74 » Instruction set mapping for performance optimization |
PPOPP
2009
ACM
16 years 4 months ago
2009
ACM
This paper proposes a new parallel execution model where programmers augment a sequential program with pieces of code called serializers that dynamically map computational operati...
131
Voted
IPCCC
2006
IEEE
15 years 9 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
139
Voted
LCTRTS
2004
Springer
15 years 8 months ago
2004
Springer
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
119
Voted
CASES
2001
ACM
15 years 7 months ago
2001
ACM
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
100
Voted
EDBT
2009
ACM
15 years 10 months ago
2009
ACM
In a variety of applications, ranging from data integration to distributed query evaluation, there is a need to obtain sets of data items from several sources (peers) and compute ...