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» Instruction set mapping for performance optimization
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CODES
2008
IEEE
15 years 6 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
AAAI
2008
15 years 2 months ago
Efficient Optimization of Information-Theoretic Exploration in SLAM
We present a novel method for information-theoretic exploration, leveraging recent work on mapping and localization. We describe exploration as the constrained optimization proble...
Thomas Kollar, Nicholas Roy
ICDE
2005
IEEE
122views Database» more  ICDE 2005»
16 years 1 months ago
Uncovering Database Access Optimizations in the Middle Tier with TORPEDO
A popular architecture for enterprise applications is one of a stateless object-based server accessing persistent data through Object-Relational mapping software. The reported ben...
Bruce E. Martin
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
15 years 8 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
DAC
1994
ACM
15 years 3 months ago
MIST - A Design Aid for Programmable Pipelined Processors
-- In this paper, a tool to aid pipelined processor instruction set implementation is described. The purpose of the tool is to choose from among design alternatives a design that m...
Albert E. Casavant