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» Instruction set mapping for performance optimization
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ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 8 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
ASPLOS
2000
ACM
15 years 7 months ago
Architectural Support for Fast Symmetric-Key Cryptography
The emergence of the Internet as a trusted medium for commerce and communication has made cryptography an essential component of modern information systems. Cryptography provides ...
Jerome Burke, John McDonald, Todd M. Austin
127
Voted
ICCD
2003
IEEE
115views Hardware» more  ICCD 2003»
16 years 10 days ago
Reducing Compilation Time Overhead in Compiled Simulators
Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead ma...
Mehrdad Reshadi, Nikil D. Dutt
125
Voted
GECCO
2008
Springer
126views Optimization» more  GECCO 2008»
15 years 4 months ago
Swarm intelligence in e-learning: a learning object sequencing agent based on competencies
In e-learning initiatives content creators are usually required to arrange a set of learning resources in order to present them in a comprehensive way to the learner. Course mater...
Luis de Marcos, José-Javier Martínez...
152
Voted
ICDE
2011
IEEE
258views Database» more  ICDE 2011»
14 years 7 months ago
SystemML: Declarative machine learning on MapReduce
Abstract—MapReduce is emerging as a generic parallel programming paradigm for large clusters of machines. This trend combined with the growing need to run machine learning (ML) a...
Amol Ghoting, Rajasekar Krishnamurthy, Edwin P. D....