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» Instruction set mapping for performance optimization
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GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
15 years 9 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
132
Voted
HPCA
1996
IEEE
15 years 7 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
121
Voted
SIAMCOMP
2000
79views more  SIAMCOMP 2000»
15 years 3 months ago
Optimal Worst Case Formulas Comparing Cache Memory Associativity
ct Consider an arbitrary program P which is to be executed on a computer with two alternative cache memories. The rst cache has k sets and u blocks in each set, this is denoted a ...
Håkan Lennerstad, Lars Lundberg
SAC
2004
ACM
15 years 8 months ago
An optimized approach for KNN text categorization using P-trees
The importance of text mining stems from the availability of huge volumes of text databases holding a wealth of valuable information that needs to be mined. Text categorization is...
Imad Rahal, William Perrizo
119
Voted
ICASSP
2009
IEEE
15 years 10 months ago
OFDM Turbo DeCodulation with exit optimized bit loading and signal constellations
We propose the combination of Orthogonal Frequency Division Multiplexing (OFDM) and Turbo DeCodulation (TDeC) – a multiple Turbo process consisting of iterative demodulation and...
Helge Lüders, Benedikt Eschbach, Laurent Schm...