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» Instruction set mapping for performance optimization
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108
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ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
16 years 8 days ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
146
Voted
GECCO
2009
Springer
166views Optimization» more  GECCO 2009»
15 years 10 months ago
Genetic programming in the wild: evolving unrestricted bytecode
We describe a methodology for evolving Java bytecode, enabling the evolution of extant, unrestricted Java programs, or programs in other languages that compile to Java bytecode. B...
Michael Orlov, Moshe Sipper
ESTIMEDIA
2005
Springer
15 years 9 months ago
Custom Processor Design Using NISC: A Case-Study on DCT algorithm
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
Bita Gorjiara, Daniel D. Gajski
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
15 years 8 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson
112
Voted
AAAI
2008
15 years 5 months ago
Learning to Analyze Binary Computer Code
We present a novel application of structured classification: identifying function entry points (FEPs, the starting byte of each function) in program binaries. Such identification ...
Nathan E. Rosenblum, Xiaojin Zhu, Barton P. Miller...