Sciweavers

369 search results - page 47 / 74
» Instruction set mapping for performance optimization
Sort
View
CC
2003
Springer
15 years 7 months ago
Early Control of Register Pressure for Software Pipelined Loops
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
Sid Ahmed Ali Touati, Christine Eisenbeis
263
Voted
GIS
2006
ACM
16 years 3 months ago
Optimization of multiple continuous queries over streaming satellite data
Remotely sensed data, in particular satellite imagery, play many important roles in environmental applications and models. In particular applications that study (rapid) changes in...
Quinn Hart, Michael Gertz
CASES
2007
ACM
15 years 6 months ago
Rethinking custom ISE identification: a new processor-agnostic method
The last decade has witnessed the emergence of the Application Specific Instruction-set Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user...
Ajay K. Verma, Philip Brisk, Paolo Ienne
CODES
2005
IEEE
15 years 7 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
FPGA
2007
ACM
119views FPGA» more  FPGA 2007»
15 years 8 months ago
Synthesis of an application-specific soft multiprocessor system
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
Jason Cong, Guoling Han, Wei Jiang