369 search results - page 64 / 74 » Instruction set mapping for performance optimization |
DAC
2008
ACM
16 years 23 days ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
ICCAD
2007
IEEE
15 years 8 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
104
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ECCV
2004
Springer
15 years 5 months ago
2004
Springer
The null space of the within-class scatter matrix is found to express most discriminative information for the small sample size problem (SSSP). The null space-based LDA takes full ...
ICPPW
2003
IEEE
15 years 5 months ago
2003
IEEE
Gaussian Cubes (GCs) are a family of interconnection topologies in which the interconnection density and algorithmic efficiency are linked by a common parameter, the variation of ...
100
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FCCM
2002
IEEE
15 years 4 months ago
2002
IEEE
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...