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» Instruction set mapping for performance optimization
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ASPDAC
2006
ACM
126views Hardware» more  ASPDAC 2006»
15 years 5 months ago
A novel instruction scratchpad memory optimization method based on concomitance metric
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated tha...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
IEEEPACT
2008
IEEE
15 years 6 months ago
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
Katherine E. Coons, Behnam Robatmili, Matthew E. T...
ICCAD
1997
IEEE
162views Hardware» more  ICCAD 1997»
15 years 4 months ago
Application-driven synthesis of core-based systems
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 4 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ICS
2007
Tsinghua U.
15 years 6 months ago
Performance driven data cache prefetching in a dynamic software optimization system
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
Jean Christophe Beyler, Philippe Clauss