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VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
15 years 9 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
SAC
2002
ACM
14 years 9 months ago
Dynamically generating web application fragments from page templates
Web-based applications are typically required to be highly customizable and configurable. New application requirements have to be introduced rapidly, often without stopping the ru...
Uwe Zdun
GLOBECOM
2008
IEEE
15 years 4 months ago
MILSA: A Mobility and Multihoming Supporting Identifier Locator Split Architecture for Naming in the Next Generation Internet
— Naming and addressing are important issues for Next Generation Internet (NGI). In this paper, we discuss a new Mobility and Multihoming supporting Identifier Locator Split Arch...
Jianli Pan, Subharthi Paul, Raj Jain, Mic Bowman
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 6 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
IPPS
2003
IEEE
15 years 2 months ago
The CoGenT Project: Co-Generating Compilers and Simulators for Dynamically Compiled Languages
To understand the performance of modern Java systems one must observe execution in the context of specific architectures. It is also important that we make these observations usi...
J. Eliot B. Moss, Charles C. Weems, Timothy Richar...