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111
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ATS
2005
IEEE
164views Hardware» more  ATS 2005»
15 years 4 months ago
A Family of Logical Fault Models for Reversible Circuits
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. H...
ISSS
1995
IEEE
96views Hardware» more  ISSS 1995»
15 years 6 months ago
Time-constrained code compaction for DSPs
{DSP algorithms in most cases are subject to hard real-time constraints. In case of programmable DSP processors, meeting those constraints must be ensured by appropriate code gener...
Rainer Leupers, Peter Marwedel
MEMOCODE
2003
IEEE
15 years 7 months ago
Optimizations for Faster Execution of Esterel Programs
Several efficient compilation techniques have been recently proposed for the generation of sequential (C) code from Esterel programs. Consisting essentially in direct simulation ...
Dumitru Potop-Butucaru, Robert de Simone
111
Voted
EMSOFT
2006
Springer
15 years 6 months ago
Software partitioning for effective automated unit testing
A key problem for effective unit testing is the difficulty of partitioning large software systems into appropriate units that can be tested in isolation. We present an approach th...
Arindam Chakrabarti, Patrice Godefroid
CAV
2000
Springer
89views Hardware» more  CAV 2000»
15 years 7 months ago
Tuning SAT Checkers for Bounded Model Checking
Abstract. Bounded Model Checking based on SAT methods has recently been introduced as a complementary technique to BDD-based Symbolic Model Checking. The basic idea is to search fo...
Ofer Strichman