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HIPEAC
2007
Springer
16 years 24 days ago
Fetch Gating Control Through Speculative Instruction Window Weighting
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...
Hans Vandierendonck, André Seznec
HIPEAC
2007
Springer
16 years 24 days ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
LCTRTS
2007
Springer
16 years 23 days ago
SWL: a search-while-load demand paging scheme with NAND flash memory
As mobile phones become increasingly multifunctional, the number and size of applications installed in phones are rapidly increasing. Consequently, mobile phones require more hard...
Jihyun In, Ilhoon Shin, Hyojun Kim
189
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LCTRTS
2007
Springer
16 years 23 days ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
PEPM
2007
ACM
16 years 23 days ago
Bidirectional interpretation of XQuery
XQuery is a powerful functional language to query XML data. This paper presents a bidirectional interpretation of XQuery to address the problem of updating XML data through materi...
Dongxi Liu, Zhenjiang Hu, Masato Takeichi
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