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DAC
2009
ACM
16 years 4 months ago
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
Lang Lin, Wayne P. Burleson
105
Voted
DAC
2009
ACM
16 years 4 months ago
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic t...
Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang
DAC
2009
ACM
16 years 4 months ago
Double patterning lithography friendly detailed routing with redundant via consideration
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
Kun Yuan, Katrina Lu, David Z. Pan
126
Voted
DAC
2008
ACM
16 years 4 months ago
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
131
Voted
DAC
2008
ACM
16 years 4 months ago
Type-matching clock tree for zero skew clock gating
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-...
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