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132
Voted
DAC
2005
ACM
16 years 4 months ago
2005
ACM
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
134
Voted
DAC
2005
ACM
16 years 4 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
127
click to vote
DAC
2006
ACM
16 years 4 months ago
2006
ACM
Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimize...
105
click to vote
DAC
2006
ACM
16 years 4 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
131
click to vote
DAC
2006
ACM
16 years 4 months ago
2006
ACM
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...