As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
The paper describes the design and the Java implementation of a coordination architecture for mobile agents, based on an object-oriented Linda-like tuple space model, compliant wi...
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
We introduce a secure architecture called an attested meter for advanced metering that supports large-scale deployments, flexible configurations, and enhanced protection for consu...
Michael LeMay, George Gross, Carl A. Gunter, Sanja...
In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, ...