Sciweavers

6593 search results - page 326 / 1319
» Integrated Learning Architectures
Sort
View
CSC
2010
15 years 4 months ago
An Evaluation of Parallel Knapsack Algorithms on Multicore Architectures
Emergence of chip multiprocessor systems has dramatically increased the performance potential of computer systems. Since the amount of exploited parallelism is directly influenced ...
Hammad Rashid, Clara Novoa, Apan Qasem
179
Voted
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
15 years 4 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
TCAD
2010
154views more  TCAD 2010»
15 years 27 days ago
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
Fu-Wei Chen, Yi-Yu Liu
ASPDAC
2012
ACM
290views Hardware» more  ASPDAC 2012»
14 years 1 months ago
CODA: A concurrent online delay measurement architecture for critical paths
With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive desi...
Yubin Zhang, Haile Yu, Qiang Xu
CVPR
2004
IEEE
16 years 8 months ago
Automatic Cascade Training with Perturbation Bias
Face detection methods based on a cascade architecture have demonstrated fast and robust performance. Cascade learning is aided by the modularity of the architecture in which node...
Jie Sun, James M. Rehg, Aaron F. Bobick