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IPPS
2000
IEEE
15 years 7 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
116
Voted
CASES
2004
ACM
15 years 8 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
SBCCI
2005
ACM
132views VLSI» more  SBCCI 2005»
15 years 9 months ago
Design and power optimization of CMOS RF blocks operating in the moderate inversion region
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...
Leonardo Barboni, Rafaella Fiorelli
RECOMB
2010
Springer
15 years 1 months ago
Predicting Nucleosome Positioning Using Multiple Evidence Tracks
Abstract. We describe a probabilistic model, implemented as a dynamic Bayesian network, that can be used to predict nucleosome positioning along a chromosome based on one or more g...
Sheila M. Reynolds, Zhiping Weng, Jeff A. Bilmes, ...
207
Voted
TSMC
2010
14 years 10 months ago
Distributed Explicit Rate Schemes in Multi-Input-Multi-Output Network Systems
Abstract--With the ever-increasing wireless/wired data applications recently, considerable efforts have focused on the design of distributed explicit rate flow control schemes for ...
Naixue Xiong, Athanasios V. Vasilakos, Laurence Ti...