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MSE
1999
IEEE
118views Hardware» more  MSE 1999»
15 years 2 months ago
Training IP Creators and Integrators
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
MM
2010
ACM
125views Multimedia» more  MM 2010»
14 years 10 months ago
Tenor: making coding practical from servers to smartphones
It has been theoretically shown that performing coding in networked systems, including Reed-Solomon codes, fountain codes, and random network coding, has a clear advantage with re...
Hassan Shojania, Baochun Li
DAC
2003
ACM
15 years 11 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
IPSN
2009
Springer
15 years 4 months ago
Recovering temporal integrity with Data Driven Time Synchronization
Data Driven Time Synchronization (DDTS) provides synchronization across sensors by using underlying characteristics of data collected by an embedded sensing system. We apply the c...
Martin Lukac, Paul Davis, Robert Clayton, Deborah ...
MSWIM
2005
ACM
15 years 3 months ago
Using statistical design of experiments for analyzing mobile ad hoc networks
The performance of mobile ad hoc networks can be influenced by numerous factors, including protocol design at every layer; parameter settings such as retransmission limits and ti...
Michael W. Totaro, Dmitri D. Perkins