27 search results - page 5 / 6 » Integrated placement and skew optimization for rotary clocki... |
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
63
Voted
ISQED
2008
IEEE
15 years 3 months ago
2008
IEEE
– As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was ...
73
Voted
TCAD
2008
14 years 9 months ago
2008
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
74
Voted
DAC
2004
ACM
15 years 10 months ago
2004
ACM
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...