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ICCAD
1994
IEEE
105views Hardware» more  ICCAD 1994»
15 years 3 months ago
Register assignment through resource classification for ASIP microcode generation
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
Clifford Liem, Trevor C. May, Pierre G. Paulin
GECCO
2006
Springer
206views Optimization» more  GECCO 2006»
15 years 3 months ago
A dynamically constrained genetic algorithm for hardware-software partitioning
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
Pierre-André Mudry, Guillaume Zufferey, Gia...
DSD
2006
IEEE
131views Hardware» more  DSD 2006»
15 years 3 months ago
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
Christian Neeb, Norbert Wehn
DSOM
1999
Springer
15 years 3 months ago
Integrating Service and Network Management Components for Service Fulfilment
: Solutions in the network and service management layers of telecommunications management architectures are currently fragmented both in terms of standards and products. It is ofte...
David Lewis, Chris Malbon, George Pavlou, Costas S...
DAC
2005
ACM
15 years 1 months ago
Matlab as a development environment for FPGA design
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algo...
Tejas M. Bhatt, Dennis McCain