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HPCA
2009
IEEE
16 years 5 days ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
135
Voted
DAC
2010
ACM
15 years 3 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
115
Voted
ICRA
2000
IEEE
163views Robotics» more  ICRA 2000»
15 years 3 months ago
The Anthropomorphic Biped Robot BIP2000
This paper describes the progress of the BIP2000 project. This project, in which four laboratories are involved for 4 years, as uimed at the realization of the lower part of an an...
Bernard Espiau, Philippe Sardain
111
Voted
QNS
1996
15 years 28 days ago
Real Inferno
Inferno is an operating system well suited to applications that need to be portable, graphical, and networked. This paper describes the fundamental oating point facilities of the...
Eric Grosse
INTERNET
2007
105views more  INTERNET 2007»
14 years 11 months ago
Workflow Planning on a Grid
evel of abstraction, we can represent a workflow as a directed graph with operators (or tasks) at the vertices (see Figure 1). Each operator takes inputs from data sources or from ...
Craig W. Thompson, Wing Ning Li, Zhichun Xiao