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ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
15 years 8 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
CISIS
2007
IEEE
15 years 1 days ago
Gridifying IBM's Generic Log Adapter to Speed-Up the Processing of Log Data
Problem determination in today's computing environments consumes between 30 and 70% of an organization’s IT resources and represents from one third to one half of their tot...
Claudi Paniagua, Fatos Xhafa, Thanasis Daradoumis
DASFAA
2003
IEEE
106views Database» more  DASFAA 2003»
15 years 5 months ago
Discovering Direct and Indirect Matches for Schema Elements
Automating schema matching is challenging. Previous approaches (e.g. [MBR01, DDH01]) to automating schema matching focus on computing direct element matches between two schemas. S...
Li Xu, David W. Embley
ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
15 years 5 months ago
Multiobjective VLSI cell placement using distributed simulated evolution algorithm
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...
Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali
ICDCSW
2003
IEEE
15 years 5 months ago
Garnet: A Middleware Architecture for Distributing Data Streams Originating in Wireless Sensor Networks
We present an architectural framework, Garnet, which a data stream centric abstraction to encourage the manipulation and exploitation of data generated in sensor networks. By prov...
Lyndell St. Ville, Peter Dickman