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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 2 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
15 years 2 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
IEEEPACT
2000
IEEE
15 years 2 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
ISLPED
2000
ACM
77views Hardware» more  ISLPED 2000»
15 years 2 months ago
A recursive algorithm for low-power memory partitioning
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
Luca Benini, Alberto Macii, Massimo Poncino
SIGSOFT
2000
ACM
15 years 2 months ago
COM revisited: tool-assisted modelling of an architectural framework
Designing architectural frameworks without the aid of formal modeling is error prone. But, unless supported by analysis, formal modeling is prone to its own class of errors, in wh...
Daniel Jackson, Kevin J. Sullivan