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DATE
1998
IEEE
91views Hardware» more  DATE 1998»
15 years 1 months ago
Interconnect Tuning Strategies for High-Performance Ics
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahu...
71
Voted
ISCA
1996
IEEE
120views Hardware» more  ISCA 1996»
15 years 1 months ago
Missing the Memory Wall: The Case for Processor/Memory Integration
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
IPPS
2000
IEEE
15 years 1 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
94
Voted
DFT
2000
IEEE
106views VLSI» more  DFT 2000»
15 years 1 months ago
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications
We present a configuration technique for a Large Area Integrated Circuit (LAIC) which is manufactured by wafer stepping. A LAIC consists of four identical subsystems, i.e., a subs...
Markus Rudack, Michael Redeker, Dieter Treytnar, O...
DEXAW
1999
IEEE
114views Database» more  DEXAW 1999»
15 years 1 months ago
A Web-Based Distributed Environment to Support Teleteaching: Design and Implementation Issues
Web based systems have been shown to be useful tools for supporting educational communication for teachers and students. In this paper we present such a system, which is an Integr...
Christos Bouras, Apostolos Gkamas, Thrasyvoulos Ts...