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ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 2 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
ISPD
2011
ACM
253views Hardware» more  ISPD 2011»
14 years 21 days ago
Assembling 2D blocks into 3D chips
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...
Johann Knechtel, Igor L. Markov, Jens Lienig
CODES
2009
IEEE
15 years 4 months ago
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
Andreas Hansson, Kees Goossens
COLCOM
2007
IEEE
14 years 11 months ago
Using context to assist the adaptation of protected multimedia content in virtual collaboration applications
—This paper proposes a framework for a virtual classroom application based on a Virtual Collaboration System (VCS), which is being developed under the VISNET II Network of Excell...
Maria Teresa Andrade, Hemantha Kodikara Arachchi, ...
IJDE
2007
123views more  IJDE 2007»
14 years 9 months ago
Identifying Authorship by Byte-Level N-Grams: The Source Code Author Profile (SCAP) Method
Source code author identification deals with identifying the most likely author of a computer program, given a set of predefined author candidates. There are several scenarios whe...
Georgia Frantzeskou, Efstathios Stamatatos, Stefan...