We present a SAT-based approach to the task and message allocation problem of distributed real-time systems with hierarchical architectures. In contrast to the heuristic approache...
To ameliorate the need to spend significant programmer time modifying parallel programs to achieve highperformance, while maintaining compact, comprehensible source codes, this pa...
In this paper we present a solution for efficient porting of sequential C++ applications on the Cell B.E. processor. We present our step-by-step approach, focusing on its general...
Ana Lucia Varbanescu, Henk J. Sips, Kenneth A. Ros...
A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. O...
Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gup...
This work presents the development of a coarse grain reconfigurable unit to be coupled to a native Java microcontroller, which is designed for an optimized execution of the embedd...