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ISCA
2007
IEEE
192views Hardware» more  ISCA 2007»
15 years 3 months ago
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
GPCE
2007
Springer
15 years 3 months ago
Debugging macros
Over the past two decades, Scheme macros have evolved into a powerful API for the compiler front-end. Like Lisp macros, their predecessors, Scheme macros expand source programs in...
Ryan Culpepper, Matthias Felleisen
IVA
2007
Springer
15 years 3 months ago
Searching for Prototypical Facial Feedback Signals
Embodied conversational agents should be able to provide feedback on what a human interlocutor is saying. We are compiling a list of facial feedback expressions that signal attenti...
Dirk Heylen, Elisabetta Bevacqua, Marion Tellier, ...
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CGO
2003
IEEE
15 years 2 months ago
Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints
Predicated execution enables the removal of branches wherein segments of branching code are converted into straight-line segments of conditional operations. An important, but gene...
Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Da...
PLDI
2003
ACM
15 years 2 months ago
Region-based hierarchical operation partitioning for multicluster processors
Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectu...
Michael L. Chu, Kevin Fan, Scott A. Mahlke