4581 search results - page 856 / 917 » Interaction design patterns for computers in sociable use |
102
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ICDCS
2007
IEEE
15 years 4 months ago
2007
IEEE
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
114
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SPAA
1995
ACM
15 years 1 months ago
1995
ACM
For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent yea...
TVCG
2010
14 years 4 months ago
2010
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...
CCGRID
2011
IEEE
14 years 1 months ago
2011
IEEE
Abstract—Parallel file systems are designed to mask the everincreasing gap between CPU and disk speeds via parallel I/O processing. While they have become an indispensable compo...
DAC
2006
ACM
15 years 11 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...