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IESS
2007
Springer
120views Hardware» more  IESS 2007»
15 years 4 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
IPPS
2005
IEEE
15 years 3 months ago
Power and Energy Profiling of Scientific Applications on Distributed Systems
Power consumption is a troublesome design constraint for emergent systems such as IBM’s BlueGene /L. If current trends continue, future petaflop systems will require 100 megawat...
Xizhou Feng, Rong Ge, Kirk W. Cameron
DRM
2005
Springer
15 years 3 months ago
DRM interoperability analysis from the perspective of a layered framework
Interoperability is currently seen as one of the most significant problems facing the digital rights management (DRM) industry. In this paper we consider the problem of interoper...
Gregory L. Heileman, Pramod A. Jamkhedkar
PLDI
2004
ACM
15 years 3 months ago
KISS: keep it simple and sequential
The design of concurrent programs is error-prone due to the interaction between concurrently executing threads. Traditional automated techniques for finding errors in concurrent ...
Shaz Qadeer, Dinghao Wu
SIGCOMM
2004
ACM
15 years 3 months ago
Network sensitivity to hot-potato disruptions
Hot-potato routing is a mechanism employed when there are multiple (equally good) interdomain routes available for a given destination. In this scenario, the Border Gateway Protoc...
Renata Teixeira, Aman Shaikh, Timothy Griffin, Geo...