This paper describes the framework of internal hardware templates. These reusable templates can be instantiated, inside the FPGA, to the required precision. Thus, the resource util...
We present a tunable representation for tracking that simultaneously encodes appearance and geometry in a manner that enables the use of mean-shift iterations for tracking. The cl...
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
Marco Facchini, Paul Marchal, Francky Catthoor, Wi...
Abstract--In linear programming (LP) decoding of a low-density parity-check (LDPC) code one minimizes a linear functional, with coefficients related to log-likelihood ratios, over ...
We provide precise high-level models for eight fundamental service interaction patterns, together with schemes for their composition into complex service-based business process int...