42 search results - page 6 / 9 » Interconnect Delay Estimation Models for Synthesis and Desig... |
105
Voted
DAC
2000
ACM
16 years 1 months ago
2000
ACM
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
104
Voted
ISPD
2003
ACM
15 years 6 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
101
Voted
VLSID
2009
IEEE
16 years 1 months ago
2009
IEEE
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
ICCAD
1994
IEEE
15 years 4 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
94
Voted
ISSS
1995
IEEE
15 years 4 months ago
1995
IEEE
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it ...