44 search results - page 4 / 9 » Interconnect design considerations for large NUCA caches |
IPPS
1998
IEEE
15 years 1 months ago
1998
IEEE
Studies of the fault-tolerance of graphs have tended to largely concentrate on classical graph connectivity. This measure is very basic, and conveys very little information for des...
CASES
2009
ACM
15 years 24 days ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
100
click to vote
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
EDBT
2010
ACM
15 years 24 days ago
2010
ACM
This paper considers the problem of Multi-Geography Route Planning (MGRP) where the geographical information may be spread over multiple heterogeneous interconnected maps. We firs...
84
Voted
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...