44 search results - page 7 / 9 » Interconnect design considerations for large NUCA caches |
ICPP
2002
IEEE
15 years 2 months ago
2002
IEEE
This work considers switching fabrics with distributed packet routing to achieve high scalability and low costs. The considered switching fabrics are based on a multistage structu...
ANCS
2009
ACM
14 years 7 months ago
2009
ACM
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
TC
2008
14 years 9 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
AAAI
1990
14 years 10 months ago
1990
Knowledge processing is very demanding on computer architectures. Knowledge processing generates subcomputation paths at an exponential rate. It is memory intensive and has high c...
MICRO
2008
IEEE
15 years 3 months ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...