816 search results - page 107 / 164 » Interconnect design methods for memory design |
VLSI
2007
Springer
15 years 3 months ago
2007
Springer
— While physically driven synthesis techniques have proven to be an effective method to meet tight timing constraints required by a design, the incremental placement step during ...
104
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RT
2004
Springer
15 years 3 months ago
2004
Springer
We introduce a tiled 3D MIP map representation of global illumination data. The representation is an adaptive, sparse octree with a “brick” at each octree node; each brick con...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
116
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SIGMOD
2012
ACM
13 years 6 days ago
2012
ACM
The advent of affordable, shared-nothing computing systems portends a new class of parallel database management systems (DBMS) for on-line transaction processing (OLTP) applicatio...