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96
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TCAD
2008
89views more  TCAD 2008»
15 years 11 days ago
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning
We present in this paper a new interconnect-driven multilevel floorplanner, called interconnect-driven multilevelfloorplanning framework (IMF), to handle large-scale buildingmodule...
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
107
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NIPS
2008
15 years 1 months ago
Designing neurophysiology experiments to optimally constrain receptive field models along parametric submanifolds
Sequential optimal design methods hold great promise for improving the efficiency of neurophysiology experiments. However, previous methods for optimal experimental design have in...
Jeremy Lewi, Robert J. Butera, David M. Schneider,...
117
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SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
15 years 5 months ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
15 years 6 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
89
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VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
16 years 26 days ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong